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STV5348 STV5348/H - STV5348/T
MONOCHIP TELETEXT AND VPS DECODER WITH 8 INTEGRATED PAGES
. . . . . . . . . . . .
COMPLETE TELETEXT AND VPS DECODER INCLUDING AN 8 PAGE MEMORY ON A SINGLE CHIP UPWARD SOFTWARE COMPATIBLE WITH PREVIOUS SGS-THOMSON's MULTICHIP SOLUTIONS (SAA5231, SDA5243, STV5345) PERFORM PDC SYSTEM A (VPS) AND PDC SYSTEM B (8/30/2) DATA STORAGE SEPARATLY DEDICATED "ERROR FREE" OUTPUT FOR VALID PDC DATA INDICATION OF LINE 23 FOR EXTERNAL USE SINGLE +5V SUPPLY VOLTAGE SINGLE 13.875MHz CRYSTAL REDUCED SET OF EXTERNAL COMPONENTS, NO EXTERNAL ADJUSTMENT OPTIMIZED NUMBER OF DIGITAL SIGNALS REDUCING EMC RADIATION HIGH DENSITY CMOS TECHNOLOGY DIGITAL DATA SLICER AND DISPLAY CLOCK PHASE LOCK LOOP 28 PIN DIP & SO PACKAGE
DIP28 (Plastic Package) ORDER CODE : STV5348 West European STV5348/H East European STV5348/T Turkish & European
SO28 (Plastic Package) ORDER CODE : STV5348D West European STV5348D/H East European STV5348D/T Turkish & European
PIN CONNECTIONS
CVBS MA/SL VDDA POL STTV/LFB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CBLK TEST VSSA VSSO XTI XTO VDDD VCR/TV RESERVED DV L23 SDA SCL Y
5348-01.EPS
DESCRIPTION The STV5348 decoder is a computer-controlled teletext device including an 8 page internal memory. Data slicing and capturing extracts the teletext information embedded in the composite video signal. Control is accomplished via a two wire serial I2C bus (R). Chip address is 22h. Internal ROM provides a character set suitable to display text using up to seven national languages. Hardware and software features allow selectable master/slave synchronization configurations. The STV5348 also supports facilities for reception and display of current level protocol data.
September 1998
FFB VSSD R G B RGB REF BLAN COR ODD/EVEN
1/22
STV5348 - STV5348/H - STV5348/T
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol CVBS MA/SL VDDA POL STTV/LFB FFB VSSD R G B RGBREF BLAN COR ODD/EVEN Y SCL SDA L23 DV RESERVED VCR/TV VDDD XTO XTI VSSO VSSA TEST CBLK Function Input Input Analog Supply Input Output / Input Input Ground Output Output Output Supply Output Output Output Output Input Input/ Output Output Output Test Input Digital Supply Crystal Output Crystal Input Ground Ground Test Input / Output Description Composite Video Signal Input through Coupling Capacitor Master/Slave Selection Mode +5V STTV / LFB / FFB Polarity Selection Composite Sync Output, Line Flyback Input Field Flyback Input Digital Ground Video Red Signal Video Green Signal Video Blue Signal DC Voltage to define RGB High Level Fast Blanking Output TTL Level Open Drain Contrast Reduction Output 25Hz Output Field synchronized for non-interlaced display Open Drain Foreground Information Output Serial Clock Input Serial Data Input/Output Line 23 Identification VPS Data Valid To be connected to VSSD through a resistor PLL Time Constant Selection +5V Oscillator Output 13.875MHz Oscillator Input 13.875MHz Oscillator Ground Analog Ground Grounded to VSSA To connect Black Level Storage Capacitor Figure 9 11 12 15 12 13 13 13 13 15 15 15 15 16 17 15 15 15 15 14 14 11 28
BLOCK DIAGRAM
STTV/LFB FFB MA/SL POL L23 5 CVBS 1 6 2 4 18
Data Clock
V DDD 22
VDDA 3
CBLK 28 VCR/TV 21 XTI 24 XTO 23 VSSO 25
CLAMPING SYNCHRONIZING DATA EXTRACTION
DATA DECODING DATA PROCESSING
Address CTRL Data
19 DV
20 TEST
OSCILLATOR FREQUENCY SYNTHETIZER TIME BASE
Data
8 PAGES MEMORY
Address CTRL
12 BLAN 13 COR 8 9 RED GREEN
SCL 16 SDA 17
I C BUS INTERFACE
2
DISPLAY INTERFACE
10 BLUE 15 Y
7 V SSD
26
27
11
14
VSSA TEST
RGB REF ODD/EVEN
2/22
5348-02.EPS
STV5348
5348-01.TBL
STV5348 - STV5348/H - STV5348/T
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI VO VDD Toper Tstg Input Voltage (any input) Output Voltage (any output) Difference between VDDD, VDDA Operating Ambient Temperature Storage Temperature Parameter Positive Supply Voltage on VDDD and VDDA Value - 0.3, 6.0 - 0.3, VDD + 0.5 - 0.3, VDD + 0.5 0.25 0, + 70 - 40, + 150 Unit V V V V
o o
C C
ELECTRICAL CHARACTERISTICS (VDD = 5V, VSS = 0V, TA = 25oC)
Symbol SUPPLIES VDD IDDD IDDA INPUTS CBLK IBLKO IBLKI CVBS CVBSI CVBSC tSYNC VCLAMP ICLPH ICLPL Video Input Amplitude (peak to peak) Input Capacitance Delay from CVBS to TCS Output from STTV Pin Clamping Level at Synchro Pulse High Level Clamp Current (CVBS = VCLAMP + 1V) Low Level Clamp Current (CVBS = VCLAMP - 0.3V) 200 0 5 - 400 1 10 V pF ns mV A A + 0.8 VDD + 10 10 V V A pF Source Current (VCBLK = 2V, VCVBS = 0V) Sink Current (VCBLK = 2V, VCVBS = 1V)) 80 - 10 A A Supply Voltage VDDD Pin Supply Current VDDA Pin Supply Current 4.75 5 30 5 5.25 V mA mA Parameter Min. Typ. Max. Unit
MA/SL, POL, LFB, FFB, VCR/TV VIL VIH IIL CI SCL, SDA VIL VIH IIL fSCL tR, tF CI RGB REF VI II Input Voltage Input Current VDD - 0.5V VDD VDD + 0.3V 50 V mA
5348-03.TBL
Input Voltage Low Level Input Voltage High Level Input Leakage Current (VI = 0 to VDDD) Input Capacitance
- 0.3 2 - 10
Input Voltage Low Level Input Voltage High Level Input Leakage Current (VI = 0 to VDD) Clock Frequency (SCL) Input Rise and Fall Time (10 to 90%) Input Capacitance
- 0.3 3 - 10
+ 1.5 VDD + 10 100 2 10
V V A kHz s pF
3/22
5348-02.TBL
STV5348 - STV5348/H - STV5348/T
ELECTRICAL CHARACTERISTICS - VDD = 5V, VSS = 0V, TA = 25oC (continued)
Symbol OUTPUTS RGB VOL VOH CL tR, tF BLAN VOL VOH CL tR, tF VOL VOH CL tR, tF VOL CL tF IOLL SDA VOL tF CL Output Low Voltage (IOL = 3mA) Fall Time (3.0 to 1.0V) Load Capacitance 0 0.5 200 400 V ns pF Output Low Voltage (IOL = 2mA) Output High Voltage (IOH = -0.2mA) Load Capacitance Rise and Fall Time (10 to 90%) Output Low Voltage(IOL = 2mA) Output High Voltage (IOH = -0.2mA) Load Capacitance Rise and Fall Time (10 to 90%) Output Low Voltage (IOL = 2mA) Load Capacitance Fall Time (RL = 1.2k, VDDD - 0.5V to 1.5V) Output Leakage Current -10 0 0 VDD - 0.8 0 VDD - 0.5 50 20 0.5 VDD 50 20 0.5 25 50 +10 0.4 V V pF ns V V pF ns V pF ns A Output Low Voltage (IOL = 2mA) Output High Voltage (IOH = -2mA, RGB REF = VDD/2) Load Capacitance Rise and Fall Time (10 to 90%) RGB REF - 0.5 0.4 RGB REF 50 20 V V pF ns Parameter Min. Typ. Max. Unit
ODD/EVEN, STTV, L23, DV
COR AND Y (with Pull up to VDDD)
CRYSTAL OSCILLATOR XTI, XTO fXTAL RBIAS CI TIMING SERIAL BUS (referred to VIH = 3V, VIL = 1.5V) tLOW tHIGH tSU, DAT tHD, DAT tSU, STO tBUF tHD, STA tSU, STA Clock : q Low Period q High Period Data Set-up Time Data Hold Time Stop Set-up Time from Clock High Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Low to High Transition s 4 4 250 170 4 4 4 4 ns ns s s s s
5348-04.TBL
Crystal Frequency Internal Bias Resistance Input Capacitance 0.4
13.875 1 3 7
MHz M pF
4/22
STV5348 - STV5348/H - STV5348/T
Figure 1 : Display Output Timing
LSP (TCS) 0 4.66 R.G.B.Y (1) 0 16.67 (a) LINE RATE 56.67 all timings in m s 40m s 64
lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced) R.G.B.Y (1) 0 41 (b) FIELD RATE 291 312 line numbers
5348-03.EPS
Figure 2 : Serial Bus Timing
SDA t BUF
t LOW
tF
SCL t HD,STA tR t HD,DAT t HIGH t SU,DAT
SDA t SU,STA
VIH = 3V , VIL = 1.5V
t SU,STO
Figure 3 : Master Synchronization Mode - Hardware Configuration
Output signal on STTV Pin : 1 Synchro Extractor Line PLL Line PLL POL grounded VCS when R1D2 = 0 TCS when R1D2 = 1 2 +5V 4 POL VCS R1D2 = "0" TCS R1D2 = "1" Bit R1D2 I2C Control POL to VDD VCS when R1D2 = 0 TCS when R1D2 = 1
MA/SL
STTV
5/22
5348-05.EPS
5348-04.EPS
STV5348 - STV5348/H - STV5348/T
Figure 4 : Master Synchronization Mode - Delivered Composite Synchronization Signal
VCS, TCS (interlaced) 621 (308) VCS, TCS (interlaced) 309 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 622 (309) 623 (310) 624 (311) 625 (312) 1 2 3 4 5 6
TCS (non-interlaced) 308 309 310 311 312 1 2 3 4 5 6
5348-06.EPS
The number positions indicate the end of lines. Internal signals : - VCS composite synchro from CVBS signal, - TCS Teletext composite synchro.
Figure 5 : Slave Synchronization Mode
MA/SL 2 +5V +5V POL 4 6 FFB POL grounded, Inputs Signals : are LFB line flyback synchro on Pin 5 FFB field flyback synchro on Pin 6 or SCS synchro composite signal on Pins 5 and 6 Note : R1D0 and R1D1 must be set to 1. POL to VDD, Inputs Signals : are LFB line flyback synchro on Pin 5 FFB field flyback synchro on Pin 6 or SCS synchro composite signal on Pins 5 and 6
5348-07.EPS 5348-08.EPS
LFB 5 SCS
Figure 6 : Data Valid Timing (DV)
Field 0 DV for VPS Data Line 16 Field 1 Field 0
6/22
STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION I - Displayable Page Memory Map The organization of a page-memory is shown in Figure 7. The display area consists of 25 rows of 40 characters per row. The organization is as follows : - Row zero contains the page header : * The first seven characters (0 - 6) are used for messages regarding the operational status. * The eighth character is an alphanumeric control character either "white" or "green" defining the "search" status of the page. When it is "white" the operational state is normal and the header appears white ; when it is "green" the operaFigure 7 : Page Memory Organization
Fixed characters Alphanumerics white for normal, green on search 7 1
tional state corresponds to the "search mode" and the header appears green. * The following twenty-four characters give the header of the requested page when the system is in search mode. * The last eight characters display the time of day. - Row number twenty-four is used by the microprocessor for the display of information, or used to display X/24 colored key data according to R0D7 bit. - Row twenty-five comprises ten bytes of control data concerning the received page (see Table 1) and fourteen free bytes which can be used by the microprocessor.
7 Status Characters
24 characters from page header rolling on page search 24
8 scrolling time characters 8
ROW
0 1 2 3 4 5 6 7 8 9 10 11
MAIN PAGE DISPLAY AREA
12 13 14 15 16 17 18 19 20 21 22 23
row free for status (R0D7 = 0) or packet X/24 (R0D7 = 1) 10 10 bytes for received page information 14 14 bytes free for use by C
24 25
5348-09.EPS
7/22
STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION (continued) II - Ghost Row Storage Organization
Row Address of Stored Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ** 0 X 0 0 X 0 0 X 0 0 X 1 Not used Designation Code 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 X / 24 X / 25 X / 28 8 / 30 * X/28 X / 27 Composition Page extension stored here if R0D7 = 0 Page extension Color definition * Broadcasting service data packet Character set designation
5348-05.TBL
Row (Packet) Number
Function
X / 26
Enhanced display facilities Page related data stored in chapter corresponding to level 1 data, i.e. For 0 goes in 4 "1 " "5 "2 " "6 "3 " "7
X / 28
Conditional access Editorial Linked pages
* Packet 8/30 storage : 8/30/0,1 : chapter 4, row23 8/30/2,3 : chapter 5, row23 8/30/4 to 15 : chapter 6, row23 ** See table 2 for VPS data storage in chapter 5
Table 1 : Row 25 Received Page Control Data Format
D0 D1 D2 D3 D4 D5 D6 D7 COLUMN PU0 PU1 PU2 PU3 HAM 0 0 0 0 PT0 PT1 PT2 PT3 HAM 0 0 0 1 MU0 MU1 MU2 MU3 HAM 0 0 0 2 MT0 MT1 MT2 C4 HAM 0 0 0 3 HU0 HU1 HU2 HU3 HAM 0 0 0 4 HT0 HT1 C5 C6 HAM 0 0 0 5 C7 C8 C9 C10 HAM 0 0 0 6 C11 C12 C13 C14 HAM 0 0 0 7 MAG0 MAG1 MAG2 0 FOUND 0 0 0 8 0 0 0 0 0 PBLF 0 0 9
5348-06.TBL
Page number : - MAG = magazine, PU = page units, PT = page tens. Page sub-code : - MU = minutes units, MT = minutes tens, HU = hours units, HT = hours tens. PBLF = page being looked for, FOUND = low for page found, HAM = hamming error in byte, C4-14 = control bits. 8/22
STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION (continued) III - VPS DATA (see Table 2) VPS data are stored in row 25 chapter 5 as shown in Table 2 when VPS enable bit (D4 of R8 register) is set. VPS data bits are decoded and stored in a received area with biphase error bit. 8/30/2 data are stored as received (without hamming decoding) in Row 23 chapter 5 according to Table 2. . 8/30 packet and VPS data decoding is the responsibility of the control software. The decoder simply stores transmitted data. IV - I2C Bus Register Map (see Table 3) Registers R0 to R10 are write only whilst R11A is Table 2 : PDC Data Storage in Chapter 5
Column VPS (Row 25) Column 8/30/2 (Row 23) VPS (Row 25) B4 B5 20 21 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
a read/write and R11B is read only. The automatic succession on a byte by byte basis is indicated by the arrows in Table 3. In the normal operating mode TB should be set to logic level 0. After power-up the contents of the registers are as follows : all bits in registers R0 to R11A are cleared to zero with the exception of bits D0 and D1 in registers R5 and R6 which are set to logical one. After power-up all the memory bytes are preset to hexadecimal value 20H (space) with the exception of the byte corresponding to row 0 of column 7 of chapter 0 which is set to the value corresponding to "alpha white" hexadecimal value 07H.
8/30/2 (Row 23) D
Initial Page
b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 B11 28 29 30 31 B12 32 33 B13 34 35 B14 36 37 B15 38 39
5348-11.TBL
Received Page Information 22 23 24 25 26 27
Status Display
Table 3 : Register Specification
D7 X24 POSITION (1) D6 D5 D4 DISABLE ROLLING HEADER GHOST ROW ENABLE ACQ. CCT A0 PRD4 (1) COR IN COR IN TOP/ BOTTOM VPS ENABLE R4 C4 D4 (R/W) 0 D3 (1) D2 EVEN OFF TCS ON START COLUMN SC2 PRD2 A2 TEXT IN TEXT IN BOX ON 24 A2 R2 C2 D2 (R/W) 0 D1 (1) D0 SEL 11B 0 FREE RUNNING PLL 7 + P/ 8 BIT BANK SELECT A2 (1) (1) BKGND IN BKGND IN CURSOR ON/OFF (1) (1) (1) D6 (R/W) 0 ACQ. ON/OFF ACQ. CCT A1 (1) (1) COR OUT COR OUT CONCEAL/ REVEAL (1) (1) C5 D5 (R/W) 0
DEW/ FULL FIELD TB
T1
T0

R0
Mode 0
R1
Mode 1
(1)
START START COLUMN COLUMN SC0 SC1 PRD1 A1 PON OUT PON OUT BOX ON 1-23 A1 R1 C1 D1 (R/W) DATA QUAL PRD0 A0 PON IN PON IN BOX ON 0 A0 R0 C0 D0 (R/W) VCS QUAL
R2 R3 R4 R5 R6 R7 R8 R9 R10 R11A R11B
Page request address Page request data Display chapter Display control (normal) Display control (newsflash / subtitle) Display mode Active chapter Active row Active column
5348-07.TBL
(1) (1) BKGND OUT BKGND OUT STATUS ROW BTM/TOP (1) (1) (1) D7 (R/W) 60Hz
PRD3 (1) TEXT OUT TEXT OUT SINGLE/ DOUBLE HEIGHT CLEAR MEM. R3 C3 D3 (R/W) 0
Active data Status
(1) Reserved register bits : must be set to 0
9/22
STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION (continued) IV - I2C Bus Register Map (continued) IV.1 - Registers Functions
Register Function Bit(s) SEL 11B (D0) EVEN OFF (D2) R0 Address 00H R11 adressing and pin functions control DISABLE ROLLING HEADER FREE RUNNING PLL (D6) X/24 POSITION (D7) T1 (D1) 0 0 1 1 T0 (D0) 0 1 0 1 Description Selection of register 11B (D0 = 1) or 11A (D0 = 0) Control of ODD/EVEN pin : EVEN signal output (D2 = 0) or grounded (D2 = 1) D4 = 1, Disable rolling header D4 = 0, Normal operation D6 = 0, PLL locks on line frequency D6 = 1, to force free running mode D7 = 0, packet X/24 stored to chapter 4 to 7/row 20 D7 = 1, packet X/24 stored to chapter 0 to 3/row 24 Character display line control : 312.5/312.5 line MIX - mode with interlace 312/313 line TEXT - mode without interlace 312/312 line Terminal mode without interlace External synchronization. SCS mode (scan field synchro) Master Mode (MA/SL Pin 2 = 0) case POL Pin 4 = 0 D2 = 0, Pin 5 = VCS D2 = 1, Pin 5 = TCS Slave Mode (MA/SL Pin 2 = VDD) No effect Selection of field flyback mode or full channel mode (D3 = 1) for recovering of Teletext data. Selection of ghost row mode (D4 = 1) Control of acquisition operation (D5 = 0 enables acquisition) Selection of received data format either 7 bits with parity (D6 = 0) or 8 bits without parity (D6 = 1). Address the first column of the on chip page request RAM to be written. Test bit equal to "0" in the normal working mode. Address a group of four consecutive pages currently used for data acquisition. Address of one of the two groups of four pages for acquisition in normal mode. Written data in the page request RAM, starting with the columns addressed by SC0,SC1,SC2. Chapter selection.
TCS ON (D2) R1 Address 01H
Operating mode controls DEW / FULLFIELD (D3) GHOST ROW ENABLE (D4) ACQUISITION ON / OFF (D5) 7 bits + parity or 8 bits without parity (D6) SC0, SC1, SC2 (D0, D1, D2)
R2 Address 02H
Addressing information for a page request
TB (D3) A0, A1 (D4, D5) A2 (D6)
R3 Address 03H R4 Address 04H
Data relative to the requested page (see Table 3) Selection of one of eight pages to display
PRD0 - PRD4 (D0 - D4) A0, A1, A2 (D0, D1, D2) PON (D0, D1)
Picture on (IN: D0, OUT: D1) Text on (IN: D2, OUT: D3) Contrast reduction on (IN: D4, OUT: D5) Background color on (IN: D6, OUT: D7) Enable inside/outside the box
5348-08.TBL
R5 Address 05H
Display control for normal operation
TEXT (D2, D3) COR (D4, D5) BKGND (D6, D7) IN / OUT
R6 Address 06H
Display control for news-flash subtitle generation
See R5
See R5
10/22
STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION (continued) IV - I2C Bus Register Map (continued) IV.1 - Registers Functions (continued)
Register Function Bit(s) BOX ON 0, 1-23,24 (D0, D1, D2) R7 Address 07H Description The "boxing" function is enabled on row 0,1-23 and 24 by D0, D1 and D2 set to one.
Display mode
TOP / BOTTOM X0 = Normal Single/ Double Height 01 = double height Rows 0 to 11 (D4/D3) 11 = double height Rows 12 to 23 Conceal / Reveal (D5) Conceal Reveal Function Cursor ON/OFF (D6) STATUS ROW BTM / TOP (D7) VPS Enable (D4) Clear Memory (D3) Chapter Address (D2, D1, D0) Cursor position given by row/column value of R9/R10 The row 24 is displayed before the "Main text Area" (lines 0-23) or after (D7 = 0). D4 = 1 Enable VPS acquisition and DV signal output. D4 = 1 Clear memory. Chapter selected with A2A1A0 (D2, D1, D0) R4. Chapter selection
R8
Memory access
R9 to R11A Address 08H to 0BH* R11B Address 0BH*
Active row address (R9), active column address (R10). Data contained in R11A read (written) from (to) memory by microprocessor via I2C. VCS QUAL (D0) Status DATA QUAL (D1) 50/60Hz (D7) Good VCS quality signal detected (D0 = 1). Bad VCS quality signal detected (D0 = 0).
5348-09.TBL 5348-10.TBL
Good TELETEXT signal (D1 = 1). Bad TELETEXT signal (D1 = 0). If D1 = 0 frame frequency is 50Hz (only valid with good VCS)
* Reading of R11A or R11B is determined by register 0, bit D0. However, write operation is always performed on R11A register.
Table 4 : Register R3
START COLUMN
PRD4 Do care magazine Do care page tens Do care page units Do care hours tens Do care hours units Do care minutes tens Do care minutes units
PRD3 HOLD PT3 PU3 X HU3 X MU3
PRD2 MAG2 PT2 PU2 X HU2 MT2 MU2
PRD1 MAG1 PT1 PU1 HT1 HU1 MT1 MU1
PRD0 MAG0 PT0 PU0 HT0 HU0 MT0 MU0
0 1 2 3 4 5 6
The abbreviations have the same significance as in Table 1 with the exception of the "DO CARE" entries. It is only when this bit is "1" that the corresponding digit is taken into consideration on page request. For example, a page defined as "normal" or one defined as "timed" may be selected. If "HOLD" is low the page is held. The addressing of successive bytes via the I C is automatic.
2
V - Character Sets The complete character set with 8-bit decoding is given in Table 5. Characters in columns 0 and 1 are normally displayed as blanks. Black dots represent the character shape whereas white dots represent the background. Each character can be identified by a pair of corresponding row and column integers : for example the character "3" may be indicated by 3/3. A rectangle may be represented as follows : The characters 8/6, 8/7, 9/5, 9/7 are used as special characters, always in conjunction with 8/5. The 13 national characters are placed in columns with bit 8 = 0.
11/22
* **
12/22
0 0
1 1 0
0
0 0
1
0 1 1 0 0 8
9 12 1
0
0 1
1
0
0 1 1 0 1
1 1 1
1 0
1 0 1 1
15 13
0
0
0 or 1 0 0 1
0
0 or 1 0
0 1
1
0 0 0 0 1
5
0 1
0 1 7
1
1 1 0
7a 6a
B I T S b4 b3 b2 b1 1
b8 b7 b6 b5 0
2a
3
0
1
3a
1
column
r o w
0
graphics black graphics re d graphics green graphics yellow graphics blue
1
2
4 6 14
0
0
0
0
0
alphanumerics black
0
0
0
1
1
alphanumerics red
0
0
1
0
2
alphanumerics green
STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION (continued)
Case using C12 C13 C14 = 001 (German Set)
graphics magenta
graphics cyan graphics white conceal display separated graphics
*
0
0
1
1
3
alphanumerics yellow
0
1
0
0
4
alphanumerics blue
0
1
0
1
5
alphanumerics magenta
Table 5 : STV5348 Complete Character Set (with 8 bit codes) - West European Languages
5348-10.EPS
These control characters are reserved for compatibility with other data codes. These control characters are presumed before each row begins
ESC
hold graphics
0
1
1
0
6
alphanumerics cyan
0
1
1
1
7
** alphanumerics white
1
0
0
0
8
flash
**
1
0
0
1
9
steady
** continuous graphics
**
1
0
1
0
10
end box
1
0
1
1
11
start box
**
1
1
0
0
12
normal height
** black background
1
1
0
1
13
double height
** new background
*
1
1
1
0
14
SO **
*
1
1
1
1
15
SI
release graphics
FUNCTIONAL DESCRIPTION (continued)
Table 6 : STV5348/H Complete Character Set (with 8 bit codes) - East European Languages
* **
0 0 1 0 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15 0 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 graphics black graphics red graphics green graphics yellow graphics blue graphics magenta graphics cyan graphics white conceal display 0 or 1 0 1 0 or 1 0 1 separated graphics * ESC hold graphics ** release graphics
0
0
0
B I T S
0
b 4 b3 b2 b1
b8 b7 b6 b5
0
column
r o w
2
0
0
0
0
0
alphanumerics black
0
0
0
1
1
alphanumerics red
0
0
1
0
2
alphanumerics green
Case using C12 C13 C14 = 001 (Rumanian Set)
0
0
1
1
3
alphanumerics yellow
0
1
0
0
4
alphanumerics blue
0
1
0
1
5
alphanumerics magenta
These control characters are reserved for compatibility with other data codes. These control characters are presumed before each row begins
0
1
1
0
6
alphanumerics c yan
0
1
1
1
7
** alphanumerics white
1
0
0
0
8
flash
**
1
0
0
1
9
steady
** continuous graphics
**
1
0
1
0
10
end box
1
0
1
1
11
start box
**
1
1
0
0
12
normal height
** black background
1
1
0
1
13
double height
** new background
*
1
1
1
0
14
SO
*
STV5348 - STV5348/H - STV5348/T
1
1
1
1
15
SI
13/22
5348-??.EPS
* **
14/22
0 0 0 0 0 1 1 1 1 0 6 6a 7 7a 8 9 12 13 14 15 1 1 1 5 0 0 0 1 1 0 0 1 0 0 1 0 1 1 1 1 0 1 1 1 1 0 0 0 4 3a 0 1 1 1 0 3 1 1 0 0 0 1 0 0 2a 2 0 0 1 1 graphics black graphics red graphics green graphics yellow graphics blue graphics magenta graphics cyan graphics white conceal display ** 0 or 1 0 1 0 or 1 0 1 separated graphics * ESC hold graphics ** release graphics
0
0
0
0
B I T S b4 b3 b 2 b 1
b8 b7 b6 b5
0
column
r o w
2
0
0
0
0
0
alphanumerics black
0
0
0
1
1
alphanumerics red
0
0
1
0
2
alphanumerics green
STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION (continued)
Case using C12 C13 C14 = 001 (German Set)
0
0
1
1
3
alphanumerics yellow
0
1
0
0
4
alphanumerics blue
0
1
0
1
5
alphanumerics magenta
Table 7 : STV5348/T Complete Character Set (with 8 bit codes) - Turkish European Languages
5348-??.EPS
These control characters are reserved for compatibility with other data codes. These control characters are presumed before each row begins
0
1
1
0
6
alphanumerics cyan
0
1
1
1
7
** alphanumerics
white
1
0
0
0
8
flash
**
1
0
0
1
9
steady
continuous graphics
**
1
0
1
0
10
end box
1
0
1
1
11
start box
**
1
1
0
0
12
normal height
** black background
1
1
0
1
13
double height
** new background
*
1
1
1
0
14
SO
*
1
1
1
1
15
SI
STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION (continued) The basic set of the 96 characters is shown in Table 8.The location of the 13 national characters Table 8 : Basic character set.
2/0 3/0 4/0
National Character
are shown in Table 8 whilst full national character sets are depicted in Tables 9, 10 and 11.
5/0
6/0
National Character
7/0
2/1
3/1
4/1
5/1
6/1
7/1
2/2
3/2
4/2
5/2
6/2
7/2
2/3
National Character
3/3
4/3
5/3
6/3
7/3
2/4
National Character
3/4
4/4
5/4
6/4
7/4
2/5
3/5
4/5
5/5
6/5
7/5
2/6
3/6
4/6
5/6
6/6
7/6
2/7
3/7
4/7
5/7
6/7
7/7
2/8
3/8
4/8
5/8
6/8
7/8
2/9
3/9
4/9
5/9
6/9
7/9
2/10
3/10
4/10
5/10
6/10
7/10
2/11
3/11
4/11
5/11
National Character
6/11
7/11
National Character
2/12
3/12
4/12
5/12
National Character
6/12
7/12
National Character
2/13
3/13
4/13
5/13
National Character
6/13
7/13
National Character
2/14
3/14
4/14
5/14
National Character
6/14
7/14
National Character
5348-11.EPS
2/15
3/15
4/15
5/15
National Character
6/15
7/15
15/22
STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION (continued) Table 9 : STV5348 Character Set - West European Languages
7/14 CHARACTER POSITION (COLUMN/ROW) C14 2/3 0 2/4 4/0 5/11 5/12 5/13 5/14 5/15 6/0 7/11 7/12 7/13
1
0
1
0
PHCB (1)
C13
0
0
1
1
0
C12
0
0
0
0
1
LANGUAGE
SWEDISH
SPANISH
ENGLISH
GERMAN
FRENCH
ITALIAN
1
0
1
Note 1 :
Where PHCB are the Page Header Control bits. Other Combinations default to English. Only the above characters change with the PHCB. All others characters in the basic set are shown in Table 5.
16/22
5348-12.EPS
STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION (continued) Table 10 : STV5348/H Character Set East European Languages
7/14
Table 11 : STV5348/T Character Set Turkish European Languages
7/14 CHARACTER POSITION (COLUMN/ROW) C14
7/13
7/12
7/11
6/0
CHARACTER POSITION (COLUMN/ROW)
5/15
5/14
5/13
5/12
5/11
4/0
2/4
2/3
C14
0
1
0
1
0
1
2/3 0
2/4
4/0
5/11
5/12
5/13
5/14
5/15
6/0
7/11
7/12
7/13
1
0
1
0
PHCB (1)
PHCB (1)
C13
C13
0
0
1
0
0
0
1
1
0
1
C12
1
C12
0
0
0
1
1
1
0
0
1
0
1
CZECHOSLOVAK
SERBO-CROAT
LANGUAGE
RUMANIAM
SWEDISH
LANGUAGE
TURKISH
POLISH
5348-??.EPS
SPANISH
ENGLISH
GERMAN
GERMAN
FRENCH
ITALIAN
1
0
1
Note 1 :
Where PHCB are the Page Header Control bits. Other Combinations default to German. Only the above characters change with the PHCB. All others characters in the basic set are shown in Table 7.
Note 1 :
Where PHCB are the Page Header Control bits. Other Combinations default to Turkish. Only the above characters change with the PHCB. All others characters in the basic set are shown in Table 7.
17/22
5348-??.EPS
STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION (continued) Figure 8 : Character Format
Alphanumerics and Graphics 'space' character 2/0
Alphanumerics character 2/13
Alphanumerics or blast-through alphanumerics character 4/8
Alphanumerics character 7/15
Contiguous graphics character 7/6
Separated graphics character 7/6
Separated graphics character 7/15 Background Color
Contiguous graphics character 7/15 Display Color
5348-17.EPS
=
=
18/22
STV5348 - STV5348/H - STV5348/T
I/O PIN ELECTRICAL SCHEMATICS Figure 9 : Analog 1 (CVBS)
VDDA
Figure 10 : Analog 2 (CBLK)
VDDA
CBLK
250W
CVBS
250W
28
1
VSSA
5348-18.EPS
VSSA
Figure 11 : Input A
VDDA 450W
Figure 12 : Input D
VDDD 450W
Pins 2, 27 MA/SL, TEST
Pins 4, 6 POL, FFB
5348-20.EPS
VSSA
VSSD
Figure 13 : PRGB
VDDD
Figure 14 : P???
VDDD
RGB REF
750kW
11
XTI 450W
XTO
450W
450W Pins 8, 9, 10 R, G, B VSSD
24
23
5348-22.EPS
VSSD
Figure 15 : INOUT
VDDD Pins 5, 12, 13, 14, 15, 18, 19, 20, 21 STTV/LFB, BLAN, COR, ODD/EVEN, Y, L23, DV, RESERVED, VCR/TV 450W
VSSD
5348-24.EPS
19/22
5348-23.EPS
5348-21.EPS
5348-19.EPS
STV5348 - STV5348/H - STV5348/T
I/O PIN ELECTRICAL SCHEMATICS (continued) Figure 16 : PSCL
VDDD SCL 450W
SDA 450W
Figure 17 : PSDA
VDDD
16
5348-25.EPS
17
5348-26.EPS
VSSD
VSSD
APPLICATION DIAGRAM
0.1m F 1 +5V SL MA 1m F +5V 3 +5V 4 5 6 7 8 9 VDDA POL STTV/LFB FFB VSSD R G VSSA 26 VSSO 25 C1* XTI 24 13.875MHz XTO 23 VDDD 22 TV VCR/TV 21 20 47kW ** 19 18 SDA 17 SCL 16 Y 15 VCR 1m F 10nF +5V C2* +5V 2 MA/SL TEST 27 CVBS CBLK 28 0.1m F
S T V 5 3 4 8
+5V 0.1m F
10 B 11 RGB REF 12 BLAN 13 COR 14 ODD/EVEN
* Value according to used crystal, C1 = C2 = 2 * CLOAD Example : C1 = C2 = 56pF, CLOAD = 30pF. ** Depending on application. Please refer to our video application lab.
Remark : all the power supply inputs must be switched on at the same time (connected to the same source).
20/22
5348-27.EPS
STV5348 - STV5348/H - STV5348/T
PACKAGE MECHANICAL DATA 28 PINS - PLASTIC DIP
Dimensions a1 b b1 b2 D E e e3 F I L
Min.
Millimeters Typ. 0.63 0.45 1.27
Max.
Min.
Inches Typ. 0.025 0.018 0.050
Max.
0.23
0.31 37.4 16.68 2.54 33.02 14.1 4.445 3.3
0.009
0.012 1.470 0.657 0.100 1.300 0.555 0.175 0.130
DIP28.TBL
15.2
0.598
21/22
PM-DIP28.EPS
STV5348 - STV5348/H - STV5348/T
PACKAGE MECHANICAL DATA 28 PINS - PLASTIC MICROPACKAGE (SO)
Dimensions A a1 b b1 C c1 D E e e3 F L S
Min. 0.1 0.35 0.23
Millimeters Typ.
Max. 2.65 0.3 0.49 0.32 45o (typ.)
Min. 0.004 0.014 0.009
Inches Typ.
Max. 0.104 0.012 0.019 0.013
0.5 17.7 10 1.27 16.51 7.4 0.4 7.6 1.27 8o (max.) 0.291 0.016 18.1 10.65 0.697 0.394
0.020 0.713 0.419 0.050 0.65
SO28.TBL
0.299 0.050
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
22/22
PM-SO28.EPS

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